Area- Delay- Power Efficient Carry Select Adder - Sareeka Deore
-25% koodilla BOOKS
Toimitus 15-21 arkipäivässä
30 päivän palautusoikeus
A main objective is proposed in this book to reduce the area and power of SQRT CSLA architecture. The condensed sum of gates by reducing the quantity of logic sources of this work pitches the great benefit in the failure of area and also the power. Therefore we get the dissimilar CSLA assembly with low area, minor power, simple and real for VLSI hardware employment. I have designed the logic tasks explained ... Täydellinen kuvaus
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Kuvaus
A main objective is proposed in this book to reduce the area and power of SQRT CSLA architecture. The condensed sum of gates by reducing the quantity of logic sources of this work pitches the great benefit in the failure of area and also the power. Therefore we get the dissimilar CSLA assembly with low area, minor power, simple and real for VLSI hardware employment. I have designed the logic tasks explained in the conventional and BEC-based CSLAs to revise the data necessity and to know dismissed logic processes. I have eradicated all those dismissed logic events of the conventional CSLA for which there is no fault arises in output and projected a new logic preparation for the CSLA. In the projected CSLA method, the CS (carry select) operation is done before the control of final-sum, this is the key difference among the conventional and proposed method.
Lisätietoja
| Kirjoittaja | Sareeka Deore |
|---|---|
| Julkaisija | LAP LAMBERT Academic Publishing |
| Julkaisuvuosi | 2024 |
| Kannen tyyppi | Pehmeäkantinen |
| EAN | 9786207456352 |