Digital Logic Design Using Verilog: Coding and RTL Synthesis - Vaibbhav Taraate
-35% koodilla BOOKS
Toimitus 17-23 arkipäivässä
30 päivän palautusoikeus
This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design conc ... Täydellinen kuvaus
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Kuvaus
This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also describes advanced RTL design concepts such as low-power design, multiple clock-domain design, and SOC-based design. The practical orientation of the book makes it ideal for training programs for practicing design engineers and for short-term vocational programs. The contents of the book will also make ita useful read for students and hobbyists.
Lisätietoja
| Kirjoittaja | Vaibbhav Taraate |
|---|---|
| Julkaisija | Springer India |
| Julkaisuvuosi | 2016 |
| Kannen tyyppi | Kovakantinen |
| EAN | 9788132227892 |