Fundamental optimized AES algorithm design in FPGA - Kailash Karande,Hrushikesh Deshpande
-35% koodilla BOOKS
Toimitus 12-18 arkipäivässä
30 päivän palautusoikeus
This book mainly focuses research in recent area of Network Security algorithm and its optimized design in area optimization domain. This book is intended for a broad range of readers who will benefits from an understanding of AES algorithm and its overall process associated with VHDL software implementation on Xilinx FPGA device. This includes students and professionals in the field of data processing and ... Täydellinen kuvaus
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Kuvaus
This book mainly focuses research in recent area of Network Security algorithm and its optimized design in area optimization domain. This book is intended for a broad range of readers who will benefits from an understanding of AES algorithm and its overall process associated with VHDL software implementation on Xilinx FPGA device. This includes students and professionals in the field of data processing and data communication, designers and implementers and data communication and networking customers and managers. This book is designed to be self ¿contained .For reader with little or more background of cryptographic algorithms.
Lisätietoja
| Kirjoittaja | Kailash Karande, Hrushikesh Deshpande |
|---|---|
| Julkaisija | LAP LAMBERT Academic Publishing |
| Julkaisuvuosi | 2016 |
| Kannen tyyppi | Pehmeäkantinen |
| EAN | 9783659863523 |