Recently, there has been a trend toward processor design based on the RISC (Reduced Instruction Set Computer) model: Example RISC processors are the MIPS, SPARC, PowerPC, ARM, and even Intel's 64-bit processor Itanium.

This guidebook provides an accessible and all-encompassing compendium on RISC processors, introducing five RISC processors: MIPS, SPARC, PowerPC, ARM, and Itanium. Initial chapters explain the differences between the CISC and RISC designs and clearly discuss the core RISC design principles. The text then integrates instruction on MIPS assembly language programming, thereby enabling readers to concretely grasp concepts and principles introduced earlier. Readers need only have a basic knowledge of any structured, high-level language to obtain the full benefits here.

Features:

*Includes MIPS simulator (SPIM) download instructions, so that readers can get hands-on assembly language programming experience

*Presents material in a manner suitable for flexible self-study

¿ Assembly language programs permit reader executables using the SPIM simulator

¿ Integrates core concepts to processor designs and their implementations

¿ Supplies extensive and complete programming examples and figures

¿ Contains chapter-by-chapter overviews and summaries

* Provides source code for the MIPS language at the book's website

Sivarama P. Dandamudi is a professor of computer science at Carleton University inOttawa, Ontario, Canada, as well as associate editor responsible for computer architecture at the International Journal of Computers and Their Applications. He has more than two decades of experience teaching about computer systems and organization. 

Key Topics

* Processor design issues

* Evolution of CISC and RISC processors

* MIPS, SPARC, PowerPC, Itanium, and ARM architectures

* MIPS assembly language

* SPIM simulator and debugger

* Conditional execution

* Floating-point and logical and shift operations

* Number systems

Computer Architecture/Programming

Beginning/Intermediate Level