Performance Optimization in Network-on-Chip: Multi Level Network Partitioning Approach - Asrani Lit,Muhamad Qaedi Edanan
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Toimitus 12-18 arkipäivässä
30 päivän palautusoikeus
The increasing complexity of System-on-Chips (SoCs) has resulted in the bottlenecking of the system due to scalability problems in the bus system. This leads to the decrement of performance of future SoCs with more complex circuitries inside them. Network-on-Chips (NoCs) was proposed as one of the solutions to overcome these issues especially regarding the communication between Intellectual Properties (IP) ... Täydellinen kuvaus
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Kuvaus
The increasing complexity of System-on-Chips (SoCs) has resulted in the bottlenecking of the system due to scalability problems in the bus system. This leads to the decrement of performance of future SoCs with more complex circuitries inside them. Network-on-Chips (NoCs) was proposed as one of the solutions to overcome these issues especially regarding the communication between Intellectual Properties (IP) in a chip. The fundamentals in designing NoC include the selection of network topologies, and hence, performance optimization is needed to ensure the full advantage of networking is taken. Therefore, multi-level Network Partitioning techniques are proposed to obtain the optimal design of networks based on its performance. The performance of a network is measured by its throughput, average queue size, waiting time and data loss. This technique is applied in a case study using MPEG-4 video application. The proposed technique is expected to enhance the performance of the NoC.
Lisätietoja
| Kirjoittaja | Asrani Lit, Muhamad Qaedi Edanan |
|---|---|
| Julkaisija | LAP LAMBERT Academic Publishing |
| Julkaisuvuosi | 2016 |
| Kannen tyyppi | Pehmeäkantinen |
| EAN | 9783659907456 |