Power Optimization in FPGA Routing circuits - Vijayan Subramaniam,Sundar Prakash Balaji Muthusamy
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Toimitus 12-18 arkipäivässä
30 päivän palautusoikeus
The work optimizes power in 4T,5T,6T,7T,8T,9T and 10T SRAM by comparing their configurations. Two mode based operations are proposed : Mode I operation and Mode-II operation. A 10T based SRAM write driver circuitry is proposed and comparison of Static Power, Static Power Dissipation, Performance metrics like Power delay product and Energy delay product are compared using TANNER 7.0. In future , Adiabatic lo ... Täydellinen kuvaus
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Kuvaus
The work optimizes power in 4T,5T,6T,7T,8T,9T and 10T SRAM by comparing their configurations. Two mode based operations are proposed : Mode I operation and Mode-II operation. A 10T based SRAM write driver circuitry is proposed and comparison of Static Power, Static Power Dissipation, Performance metrics like Power delay product and Energy delay product are compared using TANNER 7.0. In future , Adiabatic logic work circuitry has to be implemented and results are to be obtained.
Lisätietoja
| Kirjoittaja | Vijayan Subramaniam, Sundar Prakash Balaji Muthusamy |
|---|---|
| Julkaisija | LAP LAMBERT Academic Publishing |
| Julkaisuvuosi | 2018 |
| Kannen tyyppi | Pehmeäkantinen |
| EAN | 9786139896745 |